|
Circuit Description
The
c200 is a full discrete, two voltage gain stage power
amplifier derived from the classic Lin topology. The
power output stage is configured as emitter followers
and biased to class AB.
1st
Stage - the Input Differential
The input signal is fed through a network
comprising of C1,C2,R1 and R2. Input capacitor C1,
prevents DC from the preceding stage from being injected
into the input differential. C1, in combination with
R2, form a high pass filter of 3.3Hz at -3dB. R1 and
C2 serve to prevent RF from entering the input by
setting the corner frequency at 408KHz (-3dB).The
signal meets Q1 of the input differential Q1 and Q2.
Current for the differential is set by a red led constant
current source Q3 at a total of 3.0mA.
2nd
Stage - Voltage Amplifier Stage (VAS)
The amplified inverted signal is direct coupled
to the 2nd stage through Q4, which is biased into
class A by another current source Q5. In this stage,
current is set at 11.6mA by R15. Capacitor C7 (Miller
compensation) sets the dominant pole for stability.
Q4, Q5 must be heatsinked.
Vbe
Multiplier
Q6 must be connected to the main heatsink
where the power transistors are. Apart from being
a bias adjustment, it also acts as a thermal tracking
device. Prevents the output transistors from thermal
runaway. |
Output
Stage
In
order to prevent the output stage from loading the
VAS, drivers Q9 and Q10 are inserted in between to
act as buffers. Output transistors Q11,Q12,Q13 and
Q14 are configured as emitter followers operating
in class AB. Zobel network C10,R28 provides final
stability against RF oscillations. Q9-Q14 must be
connected to the main power heatsink.
Negative
Feedback
Negative feedback is global. A fraction of the output
signal is fed back into the inverted section of the
input differential via R7 and R8. Total Gain is set
at 31x or 30dB. Capacitor C3 is for high frequency
compensation whilst C4 ensures that overall dc gain
is at unity.
VI
Limiting
Over current protection is by subcircuit Q7, Q8 and
R16 through R21, including D2 and D3. It is set to
activate at load impedances of 2 ohms and below, thus
protecting the output transistors from operating out
of their SOA.
1
| 2 | 3 | 4
| 5 | 6
| 7 | 8
Next - powering
up |
